The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Wordlines are generally etched from a polysilicon-1 layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while a doped polysilicon-2 layer generally functions as the upper capacitor plate (cell plate). Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
As a result of the problems associated with the use of planar capacitors for high-density DRAM memories, all manufacturers of 4-megabit DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the typical trench capacitor, like the planar capacitor, is subject to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual polysilicon layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing both the wordline and the digitline beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
Although the stacked cell capacitor has proven to be the most manufacturable design for the four-megabit generation, trenches are generally considered to be a good bet for future generations, due to the fact that trenches can be made deeper for increased capacitance, without affecting topography of the array.
However, the continuing development of new technology makes it impossible to reliably predict the design of future DRAM generations. For example, the problem of high soft error rate characteristic of early trench designs has been solved by lining the trenches with a dielectric material prior to storage-node plate layer deposition. Furthermore, advances in stacked capacitor technology promise to make that design a participant in the 64-megabit generation. For example, complex three-dimensional structures have been created that greatly increase storage-node plate surface area. Generally, however, such structures require complex processing and multiple photomasks.
Another promising technique for increasing capacitance in DRAM cells is the use of rough polysilicon for the storage-node plate. U.S. Pat. No. (still unknown) issued to Pierre Fazan and Ruojia Lee on Aug. 27, 1991 describes a DRAM cell having a polysilicon storage-node capacitor plate which has been subjected to oxidation in order to increase the surface area thereof. Such storage-node plates are used in combination with a dielectric material such as silicon nitride, which has bulk-limited conduction characteristics, to avoid plate-to-plate current leakage. The use of such a design has resulted in cell capacitance increases of up to 35 percent. In a paper delivered to the 21st Conference on Solid State Devices and Materials in Tokyo, Japan, T. Mine, et al, describe a process for doubling the capacitance of a DRAM cell. The process involves performing an etch on a polysilicon storage-node plate layer following the deposition of a spin-on-glass layer in which are embedded photoresist particles.
Within the last several years, it has been suggested that the use of epitaxial silicon-germanium alloys might improve performance of existing semiconductor devices and possibly lead to new device structures through band gap engineering. The Department of Electrical and Computer Engineering at North Carolina State University has been active in basic research related to the use of these alloys as semiconductor materials. In Abstract No. 350 published by the 179th Electrochemical Society Meeting in Washington, D.C. in May 1991, M. Sanganeria and four colleagues report that using a rapid thermal chemical vapor deposition (RTCVD) process, selective deposition of polycrystalline Si.sub.x Ge.sub.1-x is dependent on the amount of germanium in the gas stream. However, as more germanium is added to the gas stream, the concentration of germanium in the deposited alloy, and thus the lattice mismatch between the alloy and the substrate increases, which favors a three dimensional growth. The lattice mismatch results in a rough surface morphology. Such three dimensional growth was shown to be dominant when the interfacial energy between the alloy and the substrate is greater than the sum of the alloy/ambient and substrate/ambient surface energies. At higher deposition temperatures, macroscopic islanding of the deposited alloy crystals was observed. This phenomenon has been attributed to a temperature-dependant increase in surface mobility of the depositing species. The North Carolina State University group show that deposition conditions must be optimized in order to deposit smooth polycrystalline Si.sub.x Ge.sub.1-x.